module genreg
	(clock, resetn, load, DATA, Q);
input			clock, resetn;
input			load;
input	[27:0]	DATA;
output	[27:0]	Q;

reg		[27:0]	Q;

always @(posedge clock or negedge resetn)
begin
	if (!resetn)	Q <= 0;
	else if (load)	Q <= DATA;
end

endmodule